/*
 * GICv3_gicc.h - prototypes and inline functions for GICC system register operations
 *
 * Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
 * Use, modification and redistribution of this file is subject to your possession of a
 * valid End User License Agreement for the Arm Product of which these examples are part of 
 * and your compliance with all applicable terms and conditions of such licence agreement.
 */
#ifndef GICV3_gicc_h
#define GICV3_gicc_h

/**********************************************************************/

typedef enum
{
    sreSRE = (1 << 0),
    sreDFB = (1 << 1),
    sreDIB = (1 << 2),
    sreEnable = (1 << 3)
} ICC_SREBits_t;

void setICC_SRE_EL1(ICC_SREBits_t mode);

uint64_t getICC_SRE_EL1(void);

void setICC_SRE_EL2(ICC_SREBits_t mode);

uint64_t getICC_SRE_EL2(void);

void setICC_SRE_EL3(ICC_SREBits_t mode);

uint64_t getICC_SRE_EL3(void);

/**********************************************************************/

typedef enum
{
    igrpEnable = (1 << 0),
    igrpEnableGrp1NS = (1 << 0),
    igrpEnableGrp1S = (1 << 2)
} ICC_IGRPBits_t;

void setICC_IGRPEN0_EL1(ICC_IGRPBits_t mode);

void setICC_IGRPEN1_EL1(ICC_IGRPBits_t mode);

void setICC_IGRPEN1_EL3(ICC_IGRPBits_t mode);

/**********************************************************************/

typedef enum
{
    ctlrCBPR = (1 << 0),
    ctlrCBPR_EL1S = (1 << 0),
    ctlrEOImode = (1 << 1),
    ctlrCBPR_EL1NS = (1 << 1),
    ctlrEOImode_EL3 = (1 << 2),
    ctlrEOImode_EL1S = (1 << 3),
    ctlrEOImode_EL1NS = (1 << 4),
    ctlrRM = (1 << 5),
    ctlrPMHE = (1 << 6)
} ICC_CTLRBits_t;

void setICC_CTLR_EL1(ICC_CTLRBits_t mode);

uint64_t getICC_CTLR_EL1(void);

void setICC_CTLR_EL3(ICC_CTLRBits_t mode);

uint64_t getICC_CTLR_EL3(void);

/**********************************************************************/

uint64_t getICC_IAR0(void);

uint64_t getICC_IAR1(void);

void setICC_EOIR0(uint32_t interrupt);

void setICC_EOIR1(uint32_t interrupt);

void setICC_DIR(uint32_t interrupt);

void setICC_PMR(uint32_t priority);

void setICC_BPR0(uint32_t binarypoint);

void setICC_BPR1(uint32_t binarypoint);

uint64_t getICC_BPR0(void);

uint64_t getICC_BPR1(void);

uint64_t getICC_RPR(void);

/**********************************************************************/

typedef enum
{
    sgirIRMTarget = 0,
    sgirIRMAll = (1ull << 40)
} ICC_SGIRBits_t;

void setICC_SGI0R(uint8_t aff3, uint8_t aff2,
                uint8_t aff1, ICC_SGIRBits_t irm,
                uint16_t targetlist, uint8_t intid);

void setICC_SGI1R(uint8_t aff3, uint8_t aff2,
                uint8_t aff1, ICC_SGIRBits_t irm,
                uint16_t targetlist, uint8_t intid);

void setICC_ASGI1R(uint8_t aff3, uint8_t aff2,
                uint8_t aff1, ICC_SGIRBits_t irm,
                uint16_t targetlist, uint8_t intid);

#endif /* ndef GICV3_gicc_h */
